Fabrication and characterization of a planar water gated transistor utilizing ultra thin single crystalline silicon film

In this thesis, the fabrication and characterization of a planar water-gated thin film transistor are explained and analyzed. Silicon-on-insulator (SOI) wafer is used to build the device. Two different gate structures are used and tested. Firstly, the measurements are realized with the usual probe gate immersed into the water droplet as a reference. Then the novel planar gate structure is used. In the fabrication process, first the 16-nm thick silicon on top of the SOI wafer is patterned to build the channel area of the transistor. After that aluminum is evaporated on top of it to make the drain, source and planar gate contacts at one step. Finally, photoresist is spin coated on the drain and source electrodes to insulate them from the water droplet. After forming the transistor structure, a water droplet is dripped onto the channel area. It has contact to the gate electrode and channel, but not to the drain and source electrodes. Thanks to the this liquid-solid interface, an electrical double layer is formed on the channel, which serves as a perfect gate insulator since it is uniform, pin-hole free, very thin and has a high dielectric constant. Fabricated transistors are tested and characterized. Since the silicon used is p-type, negative voltages are applied. The transistor works between 0 V and -0.7 V. Using the probe gate structure, a maximum drain current of 99.49 μA is established with an on-off ratio of 232000 and threshold voltage of 0.27 V. In the planar gate structure this values are 19.15 μA, 2150 and 0.31 V respectively. However the transistor parameters of the planar gate structure can be improved by the future developments.