Leakage current reduction in dynamic analog storage

Analog data has to be sampled and held across a capacitor prior to processing by a discrete time system. This requirement can be easily fulfilled as long as the sampling process is repeated at a sufficiently high frequency. In the case of low-frequency sampling or high temperature operation the leakage currents associated with the sampling switch may deteriorate the data held across the storage capacitor. These leakage currents are particularly significant in the 0.18-μm or newer CMOS technology nodes. We propose in this project a novel guarding technique that virtually eliminates the leakage current of an open switch by limiting port voltages to 100 μV at most. The data hold time offered by this technique is expected to be at least an order of magnitude longer than what the alternative techniques serving the same purpose can achieve. Featuring a short settling time and operating with only two unsynchronized clocks are two additional advantages offered by this technique. The only limitation on its application is the necessity of deep n-well NMOS devices.