New approaches to automated analog circuit design for robustness

This thesis presents di erent simulation-based analog circuit synthesis methodologies to obtain robust circuit synthesis and their results. HSPICE is used as simulator and SACSES is used as general methodology for mentioned simulation based approach. Three distinct methods are acquired by making modi cations in SACSES algorithm. All these three methodologies use sensitivity analyses which are done at some certain points in the process. In the rst method, achieved sensitivity results are used for calculating new costs of every individual circuit. Second and third methods are based on respectively additive and multiplicative error terms whose boundaries are attained by sensitivity analyses. Said three methods are tested on di erent three circuit topologies and results are compared. Furthermore some changes are made on SACSES and the consequences are examined.