Optimize edilmiş indirgeme devresi ile görüntü birleştirme donanım gerçeklemesi

In this thesis, the hardware implementation of a real-time image fusion algorithm using a High-Level Synthesis (HLS) tool is presented. Image fusion combines two or more images through a color transformation process. Different applications may require different frames per second (fps) and/or resolution. Yet the specifics of the image-processing algorithm may frequently change causing redesign. If the target platform is Field Programmable Gate Array (FPGA), usually rapid yet optimized hardware implementation is required. All these requirements cannot be met only by HLS. Clever approaches in terms of architectural techniques such as unorthodox ways of pipelining, coding Register Transfer Level (RTL) generators instead of RTL, and creative ways of porting interface logic/software allowed us to meet the requirements outlined above. With all these in our arsenal, we were able to get 3 versions of the image fusion algorithm (with different fps and/or resolution) running on Intel Altera Cyclone IV and Arria 10 FPGAs in a fairly short amount of time. In the image fusion algorithm, there is a standard deviation calculation, implementation of which requires accumulation of all pixel values of each frame. Hence, we designed two novel pipelined reduction circuits (and hence their RTL generators) that are named Area- Efficient Reduction Circuit (AERC) and High-Speed Area-Efficient Reduction Circuit (HSAERC). We generated several reduction circuits (AERC and HSAERC) using our own Verilog RTL generators. AERC and HSAERC designs were implemented on both Xilinx Virtex-II Pro and Virtex-5 FPGAs, and their synthesis results were compared with state-of-the-art designs in the literature. AERC design is better than the existing designs in the literature in terms of area utilization. On the other hand, HSAERC design is better than other designs in terms of performance.