Dynamic capping of waiting instruction buffer in simultaneous multi-threading processors

In simultaneous multi-threaded (SMT) systems, processors are designed to use instruction-level parallelism per thread to improve the performance of traditional superscalar processor systems. Multiple threads compete for the resources of processors to issue instructions in each cycle is the main reason for higher instruction throughput for SMT systems. Considering that threads compete for resources of the processor, utilization of critical shared resources and key datapath components is very important in SMT systems. One of the most important shared resources in SMT systems is the Waiting Instruction Buffer (WIB) or a.k.a. the Issue Queue (IQ). We need to control the WIB entry allocations of threads to be able to prevent threads from excessively allocating WIB entries which leads to decreases in overall throughput. Therefore, we determine a capping value to control the WIB entry allocation of threads. There are several approaches for resource allocation and utilization such as setting pre-defined capping values and dynamically calculating capping values for the system. In this paper, we propose a dynamic calculation of the capping value for each thread separately by using an efficiency metric based on committed instructions per resource entry. We also compare our method with previous studies which utilize WIB allocation by setting global capping value for threads in particular window sizes. With our proposed method of dynamically calculating optimum cap value, we increase the overall instruction per cycle (IPC) value and also keep fairness metric stable. For the 4-threaded system, we improve the overall IPC value of the system by an average of 7.46% and for the 8- threaded system we improve it by 9.2% while achieving better fairness result than the Lin's study.