M-seçmeli sabit-öncelikli seçme ve çoğullama

In this thesis, we propose a class of logic architectures for multi-pick (m-pick) fixed-priority arbitration (FPA) and muxing. An m-pick FPA selects the m topmost requests out of n inputs with priority order. Arbiters usually drive multiplexers (muxes). Latency optimization of FPAs and mux trees have usually been handled separately in the literature. However, in some applications with circular data dependencies, it is the combined latency of the arbiter and muxing that needs to be optimized. Moreover, there is an ever growing need for throughput. This requires, for example, network switches that pick and mux m requests per cycle, where m > 1. This thesis starts with 1-pick priority based selection and muxing and then generalizes it to m-pick. A logic building block that we call \Saturated Adder" plays a key role in this generalization, which makes the 1-pick and 2-pick architectures simply special cases. We have implemented the proposed architectures through Perl programs generating Verilog netlists and synthesized them using Synopsys Design Compiler with ARMArtisan TSMC 180 nm worst case standard-cell library. Through the results we have obtained, we demonstrated the trade-o ffs in the design of m-pick FPA and muxing.