The fast and efficient implementation of Prince algorithm on FPGAs by extending the instruction set of a processor

In this study, the Prince algorithm, which is one of the cryptographic algorithms developed to be used for IoT devices, has been implemented in an efficient way in terms of latency and resource usage criteria. The mentioned criteria are significant in almost all of the IoT applications that are used recently. In order to ensure success in the mentioned criteria, the algorithm has been implemented with Pure Register Transfer Level (RTL) design, High Level Synthesis (HLS), standard processors, and customizable processor designs. The main object of this study is to show that the customizable processor is available to meet the criteria mentioned above when the necessary changes have occurred. As a result of the studies, it has been determined that the customizable processor works more optimized than other implementations in terms of latency and resource usage balance, along with the design changes.