Applying artificial intelligence for FPGA physical design automation tools

We introduce a novel framework for predicting routing congestion in FPGA designs during the placement phase. By employing a load-balanced bi-partitioning strategy to organize the input net list, our approach enhances the accuracy of routing information prediction. Our framework incorporates carefully selected features that reflect the placement configuration and design connectivity. This clustering approach to the input net list not only improves current methodologies but also significantly improves the model's ability to predict routing congestion accurately. Additionally, this strategy enhances the routability of highly congested designs and substantially reduces router runtime. Our method achieves routability forecasting accuracy comparable to initial routing while operating at a significantly faster runtime, this address the critical need for both speed and precision in general design routability predictions. The proposed framework, which inputs well-engineered features encoded on across multiple input picture channels, shows improved performance over current techniques. This improvement is attributed to the effective partitioning of the input net list based on connectivity and bounding box. Our model is a valuable tool for early-stage FPGA routing architecture exploration, enabling rapid and accurate design iterations. It accurately predicts key routing metrics such as maximum achievable frequency (Fmax), minimum channel width (Wmin), and worst slack delay, the models' predictions exhibit correlation with full VPR CAD flow results but at a faster speed.