Development and validation of FPGA-based autorecovery logic in the CMS HGCAL data acquisition system

This thesis presents the design, implementation and validation of the FPGA-based Autorecovery Block that safeguards the data acquisition (DAQ) chain of the High Granularity Calorimeter against faulty packets and link errors. Operating at a clock frequency of 40 MHz, the Autorecovery Block monitors errors emitted by the ECON-D data concentrator ASICs. Four independent error counters track timeout, bunch crossing mismatch, event number mismatch, and buffer overflow conditions. When a counter hits its programmable threshold, the Autorecovery Block issues a recovery command. Many of the block's static parameters were converted into field-configurable ones by expanding the DAQ firmware's existing IPbus infrastructure. The error priority list, thresholds, routing map, and individual ECON-D mute status are made configurable via control registers. Status registers, on the other hand, enable monitoring of a block's internal diagnostics and support testing. The Autorecovery Block was validated on a Serenity carrier board equipped with an AMD Kintex™ UltraScale+™ KU15P Field Programmable Gate Array. The block's main functions were tested in its isolated form. The block acted on errors injected over 1024 consecutive clock cycles with 100% recovery command trigger rate. It was later embedded in a broader firmware structure and tested with emulated errors, achieving a 100% success rate again.