Design of low power continuous time σ − ∆ analog to digital converters

A second order CT Σ − ∆ modulator for audio frequency sensory systems in 180nm TSMC CMOS process is presented. The design incorporates a C-gm based current mode structure with 2nd order noise shaping, a 25 kHz bandwidth, a sampling frequency of 12.8 MHz marking an OSR of 256 and a total power consumption of 5.9$\mu$W. Consequently the proposed loop achieves a FOM of 2.8fJ/conv. The overall power consumption is distributed evenly among segments of the loop to attain adequate number of bits without the need to sacrifice power. Two representations of overall design, a robust Voltage input circuit and a high precision current input modulator, are introduced.