Content aware bitcells developed to reduce static energy dissipation for a new sram design: CSREM

Shrinking feature sizes of transistors with rising technology increase the transistor leakage currents by this alteration in sizes directly and also by effects caused by transistor density and this loop with own feedback increase the rate of the static energy dissipation on total power consumption. To this problem, at all levels in modern processors from compiler level to processor units level and then SRAM to transistor level from top to bottom there are so many techniques developed. There is still a need of transistor level solutions and designs to memory structures especially for SRAM which have high transistor density and a large proportion of processor. On account of these purposes, Content-aware Bitcells developed to reduce static energy dissipation and a novel SRAM design called CSRAM by using these bitcells will be introduced within the scope of this thesis. Suggested bitcell adapt the bias voltages to its own transistors and by this adaptive voltage regulation while storing the logic value of one or zero the threshold voltages adjusted to high. Thus, by developed Content-Aware bitcells in all cases the leakage currents are shortened effectively. Furthermore, the Simplified CSRAM bitcells; developed to unravel the case that the different body bias voltages are not allowed in some manufacturing technologies and also to get rid of the complexity of the necessary negative power supply circuitry while providing gain rates by %35 for static energy dissipation, and the Multicontent-aware CSRAM bitcells; emerged as a solution to massive rise of the area overhead when the CSRAM is used in a circuitry with small number of ports while this cost is relatively little for a one having a large number of ports, and can provide a reduction in area overhead by %6, will be mentioned in this thesis.