İki-boyutlu yarı iletkenlere dayalı nano-cihazların tasarımı ve taşıma özellikleri

As the semiconductor industry approaches the fundamental physical and electrostatic limits of traditional silicon-based transistors, the transition toward atomically thin channel materials has become imperative to sustain technological scaling. This thesis presents a proof-of-concept study on the design and transport properties of nano-devices based on two-dimensional (2D) semiconductors by evaluating their feasibility as a modular platform for next-generation nanoelectronics. Utilizing a comprehensive first-principles and quantum transport-based computational methodology that combines Density Functional Theory (DFT) with the Non-Equilibrium Green's Function (NEGF) formalism, the research systematically evaluates device performance under the ballistic transport limit. This investigation starts with Metal-Semiconductor-Metal (MSM) systems to clarify how channel length and electrode doping govern current flow at nanometer scales. The analysis then advances to p-n junctions to capture the influence of built-in electrostatics on tunneling-driven rectification. The study is followed by p-i-n field-effect transistors as intermediate architectures where gate electrodes serve as active control elements. Finally, the study is finalized with the assessment of MOSFET architectures where the integrated effects of contacts, channel transport and electrostatic control are evaluated within a unified device concept. It is evaluated that architectural optimization is as critical as material selection in the deeply scaled 2D regime. In particular, underlap engineering is identified as a practical instrument to tune source and drain electrostatics and screen drain-induced field penetration without altering the intrinsic channel material. The results demonstrate that incorporating such optimized geometries significantly boosts on-state currents and improves energy efficiency. Furthermore, these improvements enable devices to meet or surpass ITRS-2028 high-performance targets. Ultimately, this thesis presents prototype devices that demonstrate the extraordinary potential of 2D semiconductors for high-performance transistor operation when their atomically thin nature is paired with precise electrostatic engineering.