Lidar uygulamaları için 125PS LSB kolon paralel zaman-sayısal çevirici tümleşik devresi

This thesis presents a column-parallel time to digital converter (TDC) integrated circuit for light detection and ranging (LIDAR) systems. The design is based on direct time-of-flight (dToF) measurement. It is designed to be used with single-photon-avalanche photodiodes (SPAD) arrays. The TDC can measure the time differences up to 1μs with 125ps precision. This TDC design consists of four main blocks. A counter, a phase-locked loop (PLL), a delay-locked loop (DLL), and a tapped delay line (TDL) are used together to implement fine timing resolution and long-range TDC. The counter is used to increase the time difference input range. The PLL multiplies the reference clock signal frequency. PLL's voltage-controlled oscillator (VCO) is a ring oscillator that has four differential stages. The outputs of these differential stages have 45-degree phase differences, and it is used to obtain better timing resolution (similar to DLL operation). The TDL is used to achieve a fine timing resolution. It contains several series delay cells with well-defined delay times. A dedicated DLL adjusts the delay time of the cells. To have lower power consumption, the TDL has an event-driven architecture. The design is implemented in 180nm CMOS technology. The TDC has 128 columns with 26μm pixel pitch. The least significant bit (LSB) is 125ps, and the resolution is 13bit, the maximum input range results in 1024ns (150m in the distance). The INL and DNL of the system are +2/-1 LSB at maximum. The jitter noise is 8.4ps which is well below 0.5 LSB. The sampling rate is 1MS/s. The power consumption of the system (all the sub-blocks are included) is 20.5mW.