Optimization techniques used in logic circuit synthesis and a study of the optimality of synthesis results

From the 1960s to present day, the rapid pace of development in integrated circuit(IC) manufacturing technology has doubled the number of transistors that can be fitted on achip every 1.5 to 2 years. Circuit complexities have grown far beyond what is manageablewith conventional pen-and-paper based design methods, and new electronic designautomation (EDA) tools have emerged that can synthesize complete circuits from verbalbehavioral descriptions written in a Hardware Description Language (HDL).This thesis focuses on logic circuit synthesis and investigates the optimizationtechniques used by these synthesis tools. A sample circuit written in Verilog HDL has alsobeen implemented on a Spartan-3E field programmable gate array (FPGA) with Xilinx?sISE 8.2i development software, using various different optimization settings in its XSTsynthesis tool. The resulting circuits have been compared in terms of device utilization andmaximum operating speed, in order to find out how optimization settings affect thesynthesis tool?s performance.By trying out all possible combinations of a small subset of the XST settings, severalsynthesis iterations were performed. The fastest implementation that could be achievedoccupied 235 slices on the FPGA and had a maximum clock frequency of 186.78 MHz. Incomparison, the smallest implementation occupied 214 slices, but the clock frequency wasdecreased to 160.88 MHz.Synthesis results have also shown that automatic settings do not always produceoptimal results. Manual adjustments and several design iterations are necessary if theautomatic settings fail to produce a circuit meeting the design objectives, and a betterimplementation is required. Even then, a universally optimal implementation cannot beguaranteed for large designs because computational power and time restrictions prohibit anexhaustive search for the best implementation within all possible implementations.