Özel risc-V tabanli soc tasarimi: entegrasyondan isa optimizasyonuna

Soft processor cores, particularly open-source processor architectures like the RISC-V, have extended the diversity and flexibility of SoC designs, tailoring the hardware design to the software needs, instead of the opposite. These developments enable unprecedented flexibility in both hardware and software aspects, motivating the exploration of creating highly-customizable SoC integrations that can adapt to a diverse range of application requirements. The first part of this thesis begins by implementing the concept of a flexible and customizable SoC prototype, the "OzU SoC", tailored to the meet requirements of an electric metering application. The philosophy of this development work is to quickly adapt the design to its specific application needs, rather than relying solely on software optimizations on general-purpose designs. This effort culminates in implementing a prototype of the OzU SoC as a soft Intellectual Property (IP) demonstrated on a Field Programmable Gate Array (FPGA). The second part of this thesis focuses on optimizing a key challenge in modern SoC design: physical area reduction. On-chip memory, a significant factor in determining the size of modern SoC design, is the main interest. In this part, the Novel Variable-Length Inclusive Instruction Set Architecture (NOVLI-ISA) is proposed as a compatible extension to the 32-bit base integer RISC-V ISA, known as RV32I. This part includes the design, implementation, and evaluation of the proposal, with the primary goal of machine code size reduction without compromising complexity, functionality, or flexibility. This thesis demonstrates key aspects of modern customizable SoC development, contributing to the RISC-V community with the proposed extension.