Ultra-low power SAR ADC design

Analog-to-Digital Converters (ADCs) find applications in various fields. In portable applications such as the Internet of Things (IoT), power efficiency is a critical consideration. Deploying IoT devices in challenging environments introduces additional concerns, including reliability, the operating temperature range, and etc. ADCs typically serve at the front-end of an IoT device, playing a pivotal role in sensing various environmental parameters, such as temperature, pressure, and many others. The acquired data can then be processed with a Digital Signal Processor (DSP). Effectively tackling these challenges is crucial to transform theoretical concepts into tangible designs, ultimately enriching the overall user experience. Additionally, achieving high yield necessitates circuits that are robust in terms of Process, Voltage, and Temperature (PVT). In this thesis, we develop two ultra-low-power Successive Approximation Register ADCs (SAR ADCs) suitable for IoT devices in harsh environments, such as the automotive sector. Operating at sampling frequencies of 100kHz and 1MHz with VDD values of 0.7V and 1.2V, respectively, both ADCs demonstrate high robustness in the presence of PVT variations. Designed in the 65nm UMC CMOS process node, the ADC with a 0.7V supply voltage consumes only 1.55uW, while the ADC with VDD=1.2V consumes 248uW. These developments contribute to the advancement of efficient and reliable ADCs for demanding IoT applications.