Verification and enhancement of the autorecovery block and stage-1 beam test integration for CMS HGCAL detector

The Compact Muon Solenoid (CMS) detector at the Large Hadron Collider (LHC) at The European Organization for Nuclear Research (CERN) is undergoing a Phase-2 upgrade, driven by the need to ensure reliable performance under harsh radiation levels and to handle the large amount of data due to a greater number of proton-proton interactions, both brought by the increased luminosity of the High-Luminosity LHC (HL-LHC). The back-end (BE) electronics and data acquisition (DAQ) firmware are critical components of this upgrade. The BE electronics consists of field-programmable gate arrays (FPGAs), and the DAQ system is fully implemented on these programmable devices. This architecture allows for high-speed, flexible, and configurable processing of the large data streams generated during detector operation. During beam crossings, front-end (FE) application-specific integrated circuits (ASIC) that read data from on-detector sensors can become misaligned or fall out of synchronization. The Autorecovery Block is a dedicated firmware module designed to monitor error conditions and generate fast command signals to re-tune the FE electronics when necessary, thereby improving data integrity and system resilience. This thesis presents the verification, enhancement, and integration of the Autorecovery Block within the existing firmware framework. Comprehensive hardware tests were conducted using software emulators to validate its functionality. The results demonstrate that the Autorecovery Block can correctly generate the expected signals under the tested conditions, providing confidence in its readiness for future integration.