Yeniden yapılandırılabilir donanım hızlandırıcılar için yeni esnek bir yonga üstü anahtar mimarisi

This thesis work proposes ReFlex Switch, a novel, scalable on-chip packet switch architecture, that is designed to interconnect heterogeneous IP cores at high speeds. One target application for ReFlex switch is hardware accelerated cloud computing where the cloud servers feature FPGA cards with reconfigurable regions to implement accelerators demanded by the users. In this setting, the increasing data rates call for line-speed operation of the on-chip switch to maintain scalability. The first requirement of the line rate operation is a fabric arbiter design to achieve maximal throughput while allocating the switching bandwidth as required among contending traffic sources. The second requirement together with the limited on-chip memory resources is the efficient buffer management at the switch inputs. Furthermore, the service needs of the applications change with the realized accelerators on the FPGA card. ReFlex Switch fulfills these requirements with an on-chip hardware architecture that is flexibly configured according to the specified system parameters. To this end, this thesis proposes Credit ARbiter (CAR), a novel fabric arbiter with Quality of Service (QoS) support and ReFlex Buffer Management (ReFBM) a novel input buffer organization for buffer allocation to the connected cores according to their traffic demand. ReFlex Switch is implemented on Xilinx XC7Z100 SoC FPGA at 40 Gbps line rate, with CAR and ReFBM together with legacy arbiters and buffer organizations for resource use and performance comparison. The evaluations demonstrate that ReFlex switch can be flexibly instantiated with different memory parameters, arbiters and memory organizations. Furthermore, CAR and ReFBM achieve desired performance goals and outperform comparable work in the literature.