5-bit 40GS/s time interleaved analog to digital converter in 0.18µm SiGe BiCMOS technology

The A / D converters, which have higher than 10 GS/s sampling frequency, are critically important for the next generation high speed data communication. Time interleaved technique is one of the most important techniques which are used to increase sampling frequency of A / D converter above 10 GS/s. This technique utilizes the parallel connected channels which are operated in order based on the situation of the sampling signal. One of the most important circuits that determines the performance limit of the time interleaved A / D converter is the track and hold (T / H) amplifiers which holds the analog signal at specific time intervals. Another important circuit is the comparator circuit which quantizes the analog signal. Distributing sampling signals depending on their order of operation to blocks is another factor which determines the performance limit of the time interleaved A / D converter. Sampling signals decide which channel performs at a certain time for a certain time amount. Hence, if an error occurs, selected channel will not work effectively and correctly. In this study, a 5-bit 40 GS / s time interleaved A / D converter was designed in 0.18μm SiGe BiCMOS technology. The designed A / D converter consists of 4 channels. High speed parallel A / D converters are used in each channel and, switched emitter follower type T / H amplifiers are used at the front end of the structure. The digital code selection block applies to the output of the system according to situation of the sampling signal. The time interleaved A / D converter was designed in the Cadence Virtuoso 6.13 tool. Post-layout simulations are performed and results are evaluated in detail in this thesis sections. KEYWORDS: A / D converter, track and hold amplifier, SiGe BiCMOS, parallel A / D converter, time interleaved A / D converter, switched emitter follower