6-bit flash analog-to-digital converter

The purpose of this thesis is to design a converter with low power consumption andhigh sampling rate using a different structure from conventional flash analog-to-digitalconverters. The designed novel voltage comparator circuit and the following structureenable to overcome the speed problems of conventional voltage comparators. Moreover,the ROM can be driven without encoder circuit with the help of decision circuit.As in conventional Flash ADC designs, voltage comparator circuits compare inputvoltages against reference voltages in this designed Flash ADC. However, instead ofproducing a digital signal, voltage comparators produce a current at the output. The currenthas the highest value in only one voltage comparator. This current is detected by a currentcomparator which produces a digital ?1?. The outputs of voltage comparators can havevery close values at the boundaries of reference voltages. Therefore, two currentcomparators can produce ?1? at the same time. In this situation, decision circuit determinesthe highest current by the help of latch circuit. The ROM circuit can be driven withoutproducing thermometer code and encoder circuit.As a result, 6-bit, 1GS/s Flash ADC is designed in TSMC 180nm CMOS for 1.8Voperation. This converter is arranged to operate between -40° and 120°. All designsteps and details are shown in this thesis. Verification of designed circuits and all systemhas been carried out by simulations. Also, this work is compared against some of the FlashADC converters which have same technology and similar specifications, the results arepresented in this thesis.