Theses supervised by Prof. Dr. Uğur Çilingiroğlu
11 theses · Yeditepe University
A channel-leakage monitor for silicon wafer scribe testing without mechanical access
A novel sensor topology has been developed for measuring the channel leakage current of a MOSFET in scribe test. Being integrated with a wireless beacon platform powered by indoor illumination, it eliminates all aspects of mechanical access including stepping, micro-metric alignment and contact. The sensor has been developed in the form of a three-stage ring oscillator, where each stage has been built with a MOSFET device-under-test whose m segments function as the load and one segment functions as the driver. Unlike the existing ring-oscillator type leakage sensors, its frequency is not corrupted by the highly uncertain channel leakage current of any MOSFET of complementary conductance. It therefore provides the most reliable measurement among the ring-oscillator class of leakage sensors. What enables the proposed leakage sensor to eliminate the conventional mechanical access in scribe test is its nanowatt-level power consumption, which can be supplied directly by photovoltaic conversion from environmental illumination. To this end, a test monitor that integrates the sensor with a platform of photovoltaic supply and two-way communication link has been designed. Downlink has been realized with visible light communication, which enables the user to select either PMOS or the NMOS version of the sensor. Uplink has been realized with a beacon of an ultra-wide-band impulse radio. It transmits bursts of a pulse train, whose repetition rate is equal to sensor frequency. The much slower repetition frequency of the bursts is determined by the acquisition time of adequate photovoltaic energy. A small loop antenna placed approximately 1 cm above the test monitor without any critical alignment is capable of detecting the transmitted pulses.
Custom design of a fully digital true random number generator in 65-nm CMOS technology
The random number generator (RNG) is an essential component for a wide range of applications. These structures, which have been used for many years, are being developed day by day. It is one of the indispensable structures in computers and smart devices, especially in today's digital world. Many design applications, games, simulation programs, password generator programs, protected communication protocols need an RNG. RNGs are generally investigated in two different categories. The first type, pseudo-random number generator (PRNG), is often software-based and works with a deterministic algorithm. It is preferred in applications that do not require security because it can be designed easily and generate random numbers with excellent statistical properties. The second type, true random number generator (TRNG), is often used for cryptographic applications. One of the most important features to look for in the TRNG is that it produces a truly unpredictable random number sequence. Therefore, it needs a non-deterministic natural source. TRNGs use an entropy source that uses physical phenomena to meet this requirement. In this study, a custom TRNG design is presented using 65-nm CMOS technology. This design is based on metastability and is created by adding digital blocks to a structure with a dynamic comparator topology. The aim of the design is to create a circuit with a high entropy value, low power consumption, and high throughput in a small footprint as possible. It has been validated with simulations at different technology-voltage-temperature (PVT) corners to ensure that the designed circuit can operate in different conditions.
High fan-in differential capacitive-threshold-logic implementation with an offset-compensated comparator
A high fan-in threshold logic gate with a relatively low propagation delay is proposed. The gate utilizes a comparator capable of compensating the input referred offset without the need to implement a feedback loop by implementing a capacitive cross-coupling of the two inverters in the comparator. The gate performs sum-of-product and thresholding operations by individually setting the minimum sized MOSFET capacitors. This is achieved by setting the threshold and input voltages with digital logic levels. The operation of the gate is dynamic and comprises two phases, in which the inputs and threshold setting are done during the reset phase while the comparator provides the resultant at the evaluation phase. A second topology is proposed to reduce the propagation delay by implementing two more switches driven by a second clock. The thesis presents the analysis, properties, and limitations of implementing a high fan-in threshold logic gate by analyzing six gates of fan-in 15, 31, 63, 127, 255, and 511. Post-layout analysis and results of the 511 fan-in are provided. The design is then verified with CMOS 65 nm technology under all process corners with a distribution of process and mismatch of 3σ.
Digitally controllable metastability-based true random number generator
The advancement of Internet of Things (IoT) applications is driving the rapid growth and expansion of communication networks. Communication networks occur not only among individuals but also between electronic devices. The operations of encryption and decryption are extremely critical steps in the process of ensuring that communication across these networks is kept private and safe. Interest in random number generators (RNGs), which significantly impact the effectiveness of these operations, is consistently on the rise. In addition, the quality of random number generators directly affects the confidentiality of data and the effectiveness of secure communication. There are fundamentally two categories of RNGs. The first is pseudo-random number generators (PRNGs), known as deterministic RNGs, which are used in applications needing lower security. The second is true random number generators (TRNGs), which use real physical noise sources and are used in applications requiring higher safety standards. In this thesis, a digitally controlled metastability-based TRNG core is designed and fabricated using 130-nm CMOS technology. The measurement results, obtained from two separate chips at 0 °C, 50 °C, and 70 °C, demonstrate the robustness of the design. The TRNG successfully passes both AIS 31 and NIST test criteria, confirming its reliability and compliance with industry standards. Additionally, a complete TRNG design and its simulation results including the TRNG core and a proposed control algorithm is presented. It is designed for use in IoT devices, secure communication systems, smart cards, and hardware cryptographic systems. The digitally controlled nature of the TRNG ensures adaptability and resilience, making it a promising solution for modern security applications
Frequency-locked integrated CMOS oscillator design with resistive reference
The purpose of this thesis is to introduce a design for a CMOS oscillator, that is practically insensitive to temperature and line voltages and conservative in power consumption.Also presented are the details of a band-gap reference voltage reference and a beta-multiplier current reference as needed for the proper operation of the oscillator. Design and characterization of the proposed oscillator has been performed for XFAB XH018, 0.18 μm CMOS technology. The output of the oscillator provides a square wave of 545.5 kHz at room temperature with typical conditions. Oscillator output has achieved stable frequency within the temperature range -40 C 85 C and for +- 5 percent line voltage variation. The circuit satisfies the specifications by consuming only 5 μWand not more than 0.65 percent frequency variation. The design has also been verified in all process corners and distribution in process and matching for 3 sigma.
CMOS integrated selector with optical receiver and photovoltaic supply
Fabricated silicon wafers are subjected to a parametric test for identifying the ones qualified for the subsequent sort test. Also known as "scribe test", this test is performed by measuring a few basic MOSFET parameters such as threshold voltage, saturation drive current and/or channel leakage current on monitor devices placed inside scribe lines or dedicated dies. Electrical access to these devices is established by mechanical means involving stepping, micrometric alignment and contacting, which necessitate not only an expensive stepper/aligner but also a customized probe card. To overcome this expensive problem, a wireless channel-leakage monitor is proposed and got funded by TUBITAK. In this thesis, a sub-circuit for this channel-leakage monitor is designed. The integrated selector supplied by photovoltaic cells enables the communication between the silicon and the antenna and selects either PMOS or NMOS version of the monitor to be used. To this end, a compact transimpedance amplifier followed by a peak detector and a switch is designed. The circuit has no external power supply since it harvests its energy from photovoltaic cells. By enabling/disabling the flickering light source with a certain illuminance and frequency besides the ambient room light, the switch creates a 1-bit signal for the following channel-leakage monitor. With the funding from TUBITAK and using UMC 0.18 µm design kit, 2 test chips have been taped out and measured. This thesis covers all the design procedures, simulation and measurement results of this integrated selector.
6-bit flash analog-to-digital converter
The purpose of this thesis is to design a converter with low power consumption andhigh sampling rate using a different structure from conventional flash analog-to-digitalconverters. The designed novel voltage comparator circuit and the following structureenable to overcome the speed problems of conventional voltage comparators. Moreover,the ROM can be driven without encoder circuit with the help of decision circuit.As in conventional Flash ADC designs, voltage comparator circuits compare inputvoltages against reference voltages in this designed Flash ADC. However, instead ofproducing a digital signal, voltage comparators produce a current at the output. The currenthas the highest value in only one voltage comparator. This current is detected by a currentcomparator which produces a digital ?1?. The outputs of voltage comparators can havevery close values at the boundaries of reference voltages. Therefore, two currentcomparators can produce ?1? at the same time. In this situation, decision circuit determinesthe highest current by the help of latch circuit. The ROM circuit can be driven withoutproducing thermometer code and encoder circuit.As a result, 6-bit, 1GS/s Flash ADC is designed in TSMC 180nm CMOS for 1.8Voperation. This converter is arranged to operate between -40° and 120°. All designsteps and details are shown in this thesis. Verification of designed circuits and all systemhas been carried out by simulations. Also, this work is compared against some of the FlashADC converters which have same technology and similar specifications, the results arepresented in this thesis.
Active frequency multiplier by 8 mmic in SiGe HBT technology
Generation of low phase noise RF signals is crucial for a range of applications including communication systems and radars. Doppler radar is a type of radar that estimate the velocity of object by the help of Doppler effect. Slow moving objects causes small Doppler shifts relative to the fast moving objects in reflected signal's frequency. Thus resolvability of the radar is directly related to phase noise of signals. This thesis focuses on the design of low phase noise active frequency multiplier by 8 in SiGe HBT technology. Multiplier core consists three cascaded mixers which are used as a frequency doubler. The mixer topology used in this thesis is the Gilbert mixer, one of the most popular mixer topologies in the literature. This thesis also covers the design of automatic gain control loop which is used to ensure constant output power for various input power conditions.
Leakage current reduction in dynamic analog storage
Analog data has to be sampled and held across a capacitor prior to processing by a discrete time system. This requirement can be easily fulfilled as long as the sampling process is repeated at a sufficiently high frequency. In the case of low-frequency sampling or high temperature operation the leakage currents associated with the sampling switch may deteriorate the data held across the storage capacitor. These leakage currents are particularly significant in the 0.18-μm or newer CMOS technology nodes. We propose in this project a novel guarding technique that virtually eliminates the leakage current of an open switch by limiting port voltages to 100 μV at most. The data hold time offered by this technique is expected to be at least an order of magnitude longer than what the alternative techniques serving the same purpose can achieve. Featuring a short settling time and operating with only two unsynchronized clocks are two additional advantages offered by this technique. The only limitation on its application is the necessity of deep n-well NMOS devices.
A wide-supply range high-PSR bandgap voltage reference
Most precision references employ a PN junction diode voltage, since it is very predictable meaning that it does not vary significantly with process and its behavior over a given temperature range is well characterized. First-order and second-order references that base their operation on use of forward-biased diode voltage are named as bandgap references because the compensated reference output voltage is equal to or some fraction of the bandgap voltage of the material used in the process. However, since low-power consumption and low- supply levels are the main objectives of today?s IC market, classical bandgap references leave much to be desired. This thesis targets a sub-1 V bandgap voltage reference circuit that can operate in (a) a wide supply voltage range (1 - 5.5) V, (b) a wide temperature range (-40 125) °C, and still can maintain a high PSR performance while consuming a total current of only 5 µA resulting in low power consumption. The proposed circuit is designed for AMS 0.35µ C35B4C3 process.
A study of advanced encryption standard substitution-box implementations and power-analysis resistant designs
Today, the subject of symmetric-key algorithms has been extensively studied. Throughout the years, different ones have been developed, scrutinized and standardized. First wide-spread algorithm has been the Data Encryption Standard (DES) which was developed in the 1970s and standardized in 1977 by National Bureau of Standards (NBS). After DES became outdated, National Institute of Standards and Technology (NIST) announced a competition in 2001 to find a new encryption standard that would fulfill the security requirements of its time. At the end of the competition the Rijndael algorithm was selected to be the new symmetric-key algorithm standard by the name of Advanced Encryption Standard (AES). All the explained processes contribute to constant creation and testing of best algorithms mathematically possible. Nonetheless, a chain is as strong as its weakest ring and these algorithms are still being decrypted not because of their algorithmic weaknesses but because of other factors such as user-related or implementational ones. Though, excluding the glaring mistakes, some variables are harder to control. These algorithms are implemented by real devices, and real devices spend time and energy to complete the tasks they are given. These non-idealities mean that these devices leak information of what is going on inside them via electromagnetic emanations, electrical power consumption and timing delays. Therefore, a potential attacker can opt to target the non-idealities of the device rather than the algorithm. This kind of cryptographic attacks are called side-channel attacks. One of the most popular side-channel attacks is the power analysis attack. It relies on the fact that statistical properties of a device's power consumption depend on the operation and the data being operated. For AES, these attacks mostly target the substitution-boxes (S-box) because of their interesting statistical properties. Thus, this project explores different ways to implement S-boxes of AES while attempting to increase their power-analysis resistance in logic gate level.