Analog saat ağacı sentezi

Design of clock distribution circuits for Sampled Data Analog Circuits (SDACs), is a manual process that takes serious work hours and is susceptible to errors that cause silicon respins. Providing an automatic or even a semi-automatic solution to this problem will benefit the industry greatly. The equivalent problem in the digital domain, named clock tree synthesis, is fully automated, and there are commercial software that handle it. This encouraged us to work on an automated flow for the analog problem. The analog version of the problem is similar to the digital version but there are key differences. While the goal in the digital problem is to distribute a source clock to thousands of end points with zero skew, the analog problem aims to distribute a source clock to a few hundred points with deliberate skew between some end points. In the analog problem, sometimes generating divided versions of the source clock and constraining their skew with respect to the source clock may also be part of the problem. Our approach not only speeds up the design of clock circuits for SDACs but also reduces the chances of a respin. As an added benefit, it speeds up the design of analog circuit as the designer does not need to spend time to make sure the clock routes are symmetric inside the analog design. Our proposed flow has four phases, namely, requirements analysis, target determination, design \& synthesis, and verification. The first phase, requirements analysis, starts by interviewing the designer, continues with extraction of some physical parameters from the analog design, and results with a list of clock phases and timing constraints between them. The second phase of target determination has several graph-oriented tools. In this phase, we solve a specialized longest path problem efficiently to come up with a schedule of clock edges as a result that satisfies the constraints discovered in the first phase. In the third phase, we break up the clock circuit synthesis problem into two levels, namely, intrinsic and extrinsic clock trees, and drive a commercial clock tree synthesis software in an automated fashion with targets produced in the previous phase. The last phase is verification, in which we check to see if we satisfied the timing constraints we put together in the first phase. In this phase, we also do SPICE simulations and check if the circuit as a whole has acceptable figures of merit such as effective number of bits (ENOB). The conclusion is that our flow saves considerable design time and makes it less error-prone. The ENOBs obtained after our flow, when the flow is applied to a particular test design (a 10-bit 0.18 micron 2-step differential input 60 MSps Flash ADC), show that with this flow we are able to achieve ENOBs that are quite close to the best possible ENOBs under the given timing constraints. Last not but least, we have to mention that three phases of our flow (except the third one, design \& synthesis) can be used with a manual clock tree design approach to make it more systematic, hence faster and less error-prone (i.e., the semi-automatic flow).