The behoavioral modeling and an application of SAR ADC

Analog to digital converters are the main interfaces between analog world and digital circuits. The quantities which are meaningful for human senses such as voice, light, temperature etc. are not suitable for processing directly by electronic circuits. The analog values must be transformed to their electrical representations, which means the analog values are expressed as magnitude, phase or frequency of current or voltage. Finally, this information are converted to digital bits via analog to digital converters in order to be processed by digital circuits. Similarly, the digital data which consists of generally logic-1 and logic-0 are not understandable for humans. Hence, the digital to analog converters transform the bit stream to analog representations. Therefore, the need for data converters never decreases. Various types of analog to digital converter topologies are developed according to system and area requirements. Low power consumption, small area usage and design simplicity helped, SAR ADCs to become the most popular architecture at moderate speed and moderate to high resolution application in the last decades. Even though the designed ADC has physical n-bit resolution, never achieved n-bit ENOB performance in real conditions. Capacitor and transistor both arising from fabrication process, deteriorate the performance of ADC directly. The value of the capacitors affects the transfer function on the first order. Hence, the capacitor mismatch is the main limitation for high resolution ADCs. External noises which originates from electrical network, power supplies, light sources and other environmental factors such as temperature, electrical/magnetic fields are unfortunately inevitable. Also there are different internal noise and error mechanisms arise from active and passive devices. The effects of these distorting factors can be reduced using special design and fabrication techniques, but never eliminated. The obtained performance has an upper limit, no matter how successful the design. If redundancy or digital calibration techniques are used, the performance can be improved. However the power consumption and area usage increase after the application of these techniques. The purpose of the thesis is to examine the limitation of SAR ADC with and without digital calibration and redundancy. In this thesis, a differential SAR ADC model is created (with and without redundancy) in MATLAB environment in order to investigate error mechanisms and non idealities. The effects of capacitive mismatch, parasitic capacitances of DAC array, comparator noise and offset, the noise of reference voltages, sampling noise and settling behavior on ADC performance can be determined using MATLAB model. Also the optimum configuration for DAC can be chosen and, if necessary, number of the thermometric bits can be specified. This model can also be adapted easily other SAR topologies. Although this model does not include some problems such as charge injection, clock feedthrough and kickback noise, it efficiently models SAR ADCs, reducing simulation times by multiple order of magnitudes. A 14 bit differential SAR ADC is design in Cadence design environment. The design is fabricated in TSMC 65nm CMOS technology. The active die area is $2mm^2$ with full rail to rail input swing of $5V_{pp}$. A 74 dB SNDR is achieved at 20M SPS sampling rate and 5 MHz input frequency. The total power consumption is less than 25 mW from 1.2 V and 2.5 V supply voltages. In conclusion, SAR ADC performance limitations and design bottlenecks was determined thanks to the MATLAB model.The realized behavioral model will be a good start point for a designer who is dealing with SAR ADC.