Çok kalıplı FPGA yongaları için SLR tabanlı bölümleme

In recent years, transformative advancements in hardware acceleration technologies, particularly Field-Programmable Gate Arrays (FPGAs), have significantly enhanced the performance of compute-intensive applications in artificial intelligence (AI), machine learning (ML), big data analytics, and high-performance computing (HPC). However, as the scale and complexity of FPGA-based systems increase, challenges such as inter-chip communication, resource partitioning, and efficient utilization of multi-die FPGAs have become critical issues. This thesis addresses these challenges by enhancing a state-of-the-art High-Level Synthesis (HLS) compiler to support Super Logic Region (SLR) -based partitioning for multi-die FPGA chips. Key contributions include the development of a partitioning framework tailored to SLR constraints. Additionally, efficient resource utilization techniques, such as automated pipelining and bus-width conversion, are proposed to overcome timing and routing bottlenecks in multi-die architectures. The proposed methodologies are validated on Xilinx Virtex UltraScale+ FPGAs. This study contributes to advancing FPGA partitioning techniques and presents a comprehensive framework for optimizing hardware acceleration in multi-die architectures.