Dynamic allocation of physical registers in simultaneous multi-threading processors for performance, power, fairness, and quality of service

Today, Simultaneous Multi-Threading (SMT) processors allow sharing of multiple datapath elements by multiple threads. With this resource sharing, the area requirement of an SMT processor can be kept at a modest size. However, when multiple threads compete for the same resource, this kind of resource sharing can be a major problem due to resource conflicts. In an earlier study, authors propose to cap Physical Register Files (PRF) to improve performance by allocating certain PRF entries to specific threads. However, they propose a fixed-type capping mechanism which allocates a fixed amount of resource for all type of workload combinations. In this thesis, we show that optimum performance cannot be achieved by such a mechanism since resource requirements of threads can be quite variable at any time during their execution. In our first design, to improve the current state of the art, we propose a dynamically-changing PRF-capping mechanism. In this design, we track down the overall throughput and with the help of a hill climbing algorithm, we change the PRF cap size until it reaches to a near-optimal position. With this design, we achieve 8.5 percent performance improvement, on the average. Our peak performance improvement reaches to 41 percent. In our second design, we propose a dedicated PRF cap size for each thread. Simply, we assign different PRF cap size to each running thread to achieve better power/energy figures compared to our first design. We utilize Committed Instructions Per Resource Entry (CIPRE) efficiency metric to calculate the efficient-use of PRF by each thread. When a thread does not fully utilize its share on the PRF, its efficiency metric goes down and we realize that we can turn off a certain number of PRF entries which are not needed. As a result, by turning off PRF partitions we can also save power. Our experiments show that we can save almost 4 times more power compared to our first design.