Efficient hardware architectures for cryptographic algorithms used in computer and communication systems

Modern cryptography is an important discipline, which involves the disciplines of mathematics, electrical engineering and computer science, that provides the primitives of security services to information systems. Today, more important is how the fundamentals of cryptography are implemented and used. They involve significantly a series of computationally complex mathematical transformations and suffer from computational efficiency problems. Improving the security levels in computer and communication systems involves huge multiplications or performing the algorithm with longer key that might be a hundred digits long or longer, which make the computational complexity worse. In this dissertation, diverse efficient hardware architectures are proposed for a set of cryptographic algorithms, which are necessary to provide security functions to those systems, in order to overcome the computational efficiency challenges. Through the proposed design techniques, which accommodate resource sharing, efficient memory access scheme and tight scheduling, novel compact coprocessors are developed for many kinds of ciphers in symmetric and asymmetric cryptography. The proposed coprocessors focus on finding better trade-off between cost and performance and overcome the challenges introduced by the growing system needs. The proposed architectures are analyzed and compared based on hardware performance metrics consisting of area, frequency and throughput measures. The experimental results and comparisons show that the methods require very low-area with adequate throughput values for many applications. They also reveal a deeper understanding of the computational efficiency of studied cryptographic algorithms. Designing efficient hardware architectures for those algorithms solves the efficiency issues and reveals the parallelism behind the algorithm.