Efficient realtime image scaling and warping in hardware

Downscaling and warping are found in many image/video processing applications. This thesis offers an area-efficient downscaler hardware architecture and an implementation of a warping algorithm on hardware. The proposed downscaler is called "ODD (Output Domain Downscaler)". Both warping and output domain downscaler are demonstrated based on the implementation of bilinear interpolation method. Same interpolation method used in a different setting caused the difference between downscaler and warping implementations. Memory read and write methods of both warping and downscaler are also implemented with a single general FIFO. FIFO size calculation tool and a scheduler tool was used when implementing warping unit. Output domain downscaler is also combined with edge detection and sharpening spatial filter. This thesis compares output domain downscaler to a straight-forward implementation of the same combination of methods, which is called "Input Domain Downscaler". Input domain downscaler tries to output a new pixel of the downscaled video frame every time a new pixel of the original video frame is received. However, every once in a while, there is no downscaled pixel to produce. Input domain downscaler sometimes also skips a complete row of input pixels. Output domain downscaler, on the other hand, spreads out the job of producing downscaled pixels almost uniformly over a frame. As a result of that, output domain downscaler is able to do more resource sharing, i.e., can do the same job with fewer arithmetic units, thus offers a more area-efficient solution than input domain downscaler. In this thesis, output domain downscaler architecture is implemented with a downscale ratio between 1 and 2 with no loss of generality. That is because it is best to achieve larger downscale ratios of bilinear interpolation by applying a downscale ratio between 1 and 2 multiple times.