Time to digital converter design with FPGA

The Time to Digital Converter (TDC) converts the passing time between two pulse signals called as "start" and "stop" into the numerical code. Particulary, medical scanning equipments, x-rays, radars, sensors and nuclear physics are requied highly sensitive time period. therefore, it is one of the significant component in these kinds of systems. TDC can be designed with different methods such as Flash, Vernier's delay line, Vernier's ring delay line and Counter based. Counter based was used in this study. Correspondingly, FPGA was preffered in this study due to its advantages and flexibilities at digital circuits design and the ability of paralel working and effectiveness at the usage of power. FPGA was programmed with ISE Design Suite 14.7 by using VHDL. In the system design, there are a total of four signal inputs. In addition to the so-called start, stop, reset and pulse signal of the system, there is also a reset button for restarting the system. In this design, where start and stop signals are entered by the user, the simulation results of four different pulse generators, 20MHz, 40MHz, 50MHz and 66MHz, and the time-digital converter are obtained. At the same time, it was transferred to Spartan 3E starter card and its hardware implementation was realized. As a result of the simulation and hardware implementation realization, when the pulse generator of 66 MHz was used, it was observed that the minimum start time was 15 ns and the maximum end time was 65 seconds.