FPGA based graphic system design for embedded systems

In this thesis, realization of a two dimensional sequential graphic-processing system on FPGA is considered. The motivating factors in the preperation of the thesis include varying graphic needs of the embedded systems, inconveniency of commercial graphic cards for the embedded systems and their high costs, advantages that will be available to graphic systems due to the flexible configurability provided by FPGA.In the prototype work, the rasterization IP Cores, such as line drawing with BitBLT, Alpha Blending, Bresenham Method, polygon drawing and polygon filling, are implemented in VHDL. The rendering phases of model transformations and image transformations before rasterization are implemented in C language to work on embedded CPU IP Core. At the same time, graphic IP Cores are driven by CPU through C functions. As hardware Xilinx University Program Virtex-II Pro Development Kit and as development environment Xilinx EDK, ISE 7.1 are used.