Design and implementation of FPGA-based chaotic oscillator in IQ-Math number standard

Due to the non-periodic characteristics of chaos or chaotic systems, their dependence on initial conditions and system parameters, their non-periodicity in the state space, and their noise-like characteristics, engineering in recent years; The design of chaotic oscillators in areas such as cryptology, secure communication, industrial control, artificial neural networks, random number generators and image processing is of quite great importance. In this thesis, chaotic oscillators have been designed and implemented in accordance with FPGA based IQ-Math fixed point number standards with real time and maximum operating frequency. In the first stage of the thesis, the SEA chaotic system was modelled using Matlab based Euler, Heun, fourth order Runge Kutta, fifth order Runge Kutta Butcher, Dormand-Prince (DP) numerical algorithms and chaos analysis of the SEA chaotic system. Time series and phase portraits of each numerical algorithm of the SEA chaotic oscillator were investigated. The DP-based numerical model of the SEA chaotic system is more sensitive than other numerical algorithms. In the second stage of the thesis, the SEA chaotic system was coded in the VHDL language on the FPGA chip using a 32-bit IEEE 754-1985 floating-point number standard DP numerical algorithm. The design was synthesized and tested using Xilinx ISE 14.7 simulation program. The DP-based SEA chaotic oscillator was then implemented on the Xilinx Virtex-6 family XC6VLX240T-1FF1156 FPGA chip. Chip statistics and maximum operating frequency of the DP-based SEA chaotic oscillator are presented. In the third stage of the thesis, the SEA chaotic system was encoded in the VHDL language on the FPGA chip using the DP numerical algorithm in accordance with 32-bit (16I-16Q), 28-bit (14I-14Q), 24-bit (12I-12Q), 20-bit (10I-10) and 16-bit (8I- 8Q) IQ-Math fixed-point number standards. The Xilinx Virtex-6 family was tested and synthesized using Xilinx ISE 14.7 simulation program on XC6VLX240T-1FF1156 FPGA chip. The chip statistics and maximum operating frequencies of the SEA chaotic oscillators in five different fixed-point number standards were presented. In the last stage of the thesis, chip statistics and maximum operating frequencies of the SEA chaotic oscillators in five different IQ-Math fixed-point number standards and 32- bit IEEE 754-1985 floating point number standard were compared. In addition, RMSE and MSE error on the results obtained from the implementation of FPGA were performed and the results obtained from the studies were evaluated.