Devoloping a novel integrated hardware architecture for calculation of logarithmic and exponantional functions

In this work, a novel method Reduced CORDIC Based Logarithm Converter (RCBLC) is introduced for computing the specific-based logarithm of the binary values, and then the hardware architecture of RCBLC based on FPGA is analyzed in detail. Hardware architecture of RCBLC is implemented such that it enables logarithm conversion with both high output bit-sensitivity and low resource utilization. In addition to CORDIC method which includes only add-and-shift operations, using the rapid value reduction method provides an opportunity for calculating logarithm of a value more precise and lower resource utilization comparing to other methods. Thanks to the reduction method in it, RCBLC can provide wide operating input interval for logarithm conversion. Keywords: Logarithm, FPGA, CORDIC, Signal processing