Fir filter energy and performance comparison of GPU and FPGA for mobile platforms

FIR filtering is one of the most common needs of digital signal processing applications demanding linear phase response and stability. Due to the inherent parallel property of FIR filter structure, FPGAs are common solutions to implement FIR filters for embedded systems. Recently, GPGPU emerged as an effective technique for solving computation-intensive problems having massive level of parallelism. However, they are infamous with their huge power consumption. Since low power is always a requirement for mobile platforms, many-core power hungry GPGPUs seem not to be a very effective solution. Powerful FPGAs like Virtex series of Xilinx are also consume substantial amount of energy and not suitable to be utilized in mobile platforms. In this work, FIR filters of different tap sizes on Spartan 3A DSP FPGA and a mobile heterogeneous system which includes an ARM Cortex-A9 accompanying a light-weight Vivante GPU. The implemented FIR filters are compared with respect to energy consumption and throughput values. Spartan FPGA energy consumption is calculated via Xilinx?s Xpower Estimator software tool, while the heterogeneous system energy is calculated by measuring the current flowing into the heterogeneous system. Different architectures for FPGA implementation and variety of code optimizations are done for GPGPU implementation. The results show that Spartan 3A DSP FPGA outperforms the heterogeneous platform with respect to both energy efficiency and performance aspects. GPGPU is relatively a new concept with respect to FPGAs; thus, new GPGPU designs may challenge FPGAs with new emerging techniques.