A study of advanced encryption standard substitution-box implementations and power-analysis resistant designs

Today, the subject of symmetric-key algorithms has been extensively studied. Throughout the years, different ones have been developed, scrutinized and standardized. First wide-spread algorithm has been the Data Encryption Standard (DES) which was developed in the 1970s and standardized in 1977 by National Bureau of Standards (NBS). After DES became outdated, National Institute of Standards and Technology (NIST) announced a competition in 2001 to find a new encryption standard that would fulfill the security requirements of its time. At the end of the competition the Rijndael algorithm was selected to be the new symmetric-key algorithm standard by the name of Advanced Encryption Standard (AES). All the explained processes contribute to constant creation and testing of best algorithms mathematically possible. Nonetheless, a chain is as strong as its weakest ring and these algorithms are still being decrypted not because of their algorithmic weaknesses but because of other factors such as user-related or implementational ones. Though, excluding the glaring mistakes, some variables are harder to control. These algorithms are implemented by real devices, and real devices spend time and energy to complete the tasks they are given. These non-idealities mean that these devices leak information of what is going on inside them via electromagnetic emanations, electrical power consumption and timing delays. Therefore, a potential attacker can opt to target the non-idealities of the device rather than the algorithm. This kind of cryptographic attacks are called side-channel attacks. One of the most popular side-channel attacks is the power analysis attack. It relies on the fact that statistical properties of a device's power consumption depend on the operation and the data being operated. For AES, these attacks mostly target the substitution-boxes (S-box) because of their interesting statistical properties. Thus, this project explores different ways to implement S-boxes of AES while attempting to increase their power-analysis resistance in logic gate level.