Design and implementation of a synchronous addressing architecture for using in superconducting stripline detector matrix

Complementary Metal Oxide Semiconductor (CMOS) addressing circuits have some disadvantages such as operation speed and power consumption. On the other hand, Rapid Single Flux Quantum (RSFQ) technology is a promising alternative where the CMOS technology is inadequate in terms of operations speed and power consumption. In this study, we have designed a synchronous addressing circuit to observe the responses of Superconducting Stripline Detector(SSLD) Matrix. This addressing circuit contains counter circuit, demultiplexer unit and an array of Quasi-One Junction Squids(QOSs). This comparator circuit digitalizes analog input signals and forms a logic "1" output in the presence of over-threshold current in the input of the QOS. Designed addressing architecture aims to scan incoming data to detect location of incident beam. At first, counter circuit triggers the clocks of QOS circuits in a time-multiplexed fashion and then QOS outputs are transferred to the D-Flip-Flops (DFFs). These DFFs are clocked by demultiplexer unit at the frequency of external clock. Lastly, outputs of DFFs are converted to serial pulse train via merger cells. At the same time, counter circuit indicates the address of the firing pixel. After designing a 2 bit adressing circuit,we have extended it to 4 bit. 2 bit adressing circuit can operate up to 11.7 GHz while 4 bit adressing circuit can operate up to 2 GHz. 16x16 pixel image that developed using 4 bit adressing circuits can be read out at a frame rate of 1MHz.