Mitigating the effect of technological inadequacy on instruction TLB performance via generating physical addresses directly

Processor design with ever-smaller transistors leads to dramatic variations in critical transistor parameters such as channel length, threshold voltage, and gate oxide thickness. These variations manifest themselves as fluctuations in access latencies and power consumptions of the identically-designed components. A potential impact of process variation on a translation lookaside buffer (TLB) is that the different entries of the same TLB can have different access latencies. A simple way of handling this problem is to adopt the worst case latency paradigm, i.e., assume that all the TLB entries have the latency of the slowest TLB entry. While this makes the design of the logic that interacts with the TLB simpler, it can also cost significant performance penalty and we can expect this penalty to increase in the future as we go to the finer process technologies. In this study, we propose and evaluate an alternate scheme to this worst case latency paradigm. Our approach performs the virtual-to-physical page translation for a page once and stores it in a special register, which is referred to the Context Frame Register (CFR), and reuses this translation (without going to the iTLB) as long as the execution remains within the same instruction page. Since this approach minimizes the number of iTLB visits, the overall impact of process variation can be reduced dramatically; even if we assume the worst case latency if/when the iTLB is visited.Keywords : Process Variation, Address Translation, Instruction TLB (Translation Lookaside Buffer)