Time interleaved sar adc design with background calibration

Analog to digital converters are interface circuits between analog signals and digital signals. High speed analog to digital converters with moderate resolutions are used in many applications such wireless communication, optical communication, serial-link receivers, direct-sampling TV receivers and digital oscilloscopes. On the other hand, power efficient wideband ADCs are needed for many battery-powered portable devices. Increasing speed or resolution of ADCs results in power penalty. Power consumption increases nearly linearly with increasing resolution or sample rate up to process boundries. However, when approaching process boundries power consumption increases beyond linear. Time-interleaved ADCs are used to overcome the power penalty issue when the speed approaches the process boundries. Analog to digital conversion can be separated into two steps which are sampling and quantization. Time-interleaving ADCs distribute quantization step over parallel channels. This slows speed of the quantization circuit back from the process boundries. Therefore, the power efficiency is provided as if process boundries are extended to higher frequencies by the number of channels. So in time interleaved ADCs, while sampling rate is just equal to the conversion rate, quantization rate can be decreased by the number of the parallel channels. Metastability is another problem in high speed ADC circuits. As comparator speed decreases by interleaving subADCs, metastability rate also decreases by timeinterleaved architecture. Despite the benefits mentioned above, mismatch among the subADC channels can degrade linearity. Mismatch errors can be categorized into two classes: static and dynamic errors. Gain mismatch, ofset mismatch and capacitor mismatch of subADCs are static error sources. Static errors are frequency independent and dealt easier compared to dynamic errors. Dynamic errors are input frequency dependent errors which include timing skew mismatch and bandwidth mismatch errors. Dynamic mismatch errors gain dominance as input signal frequency increases and may become most dominant error source when digitizing high frequency inputs. Both static and dynamic mismatch errors can be corrected by utilizing calibration circuits. In this study, a time-interleaved ADC consisting of 18 parallel channels is designed. Sampling speed of converter is 2GS/s, 52dB SNDR is accomplished around Nyquist frequencies. Besides, digital background calibration system is designed and simulated in MATLAB and Verilog environment.