Mapping methods for three dimensional network-on-chip (3D-NOC) architectures

The number of cores in the chip has shown a rapid increase with the advancement of technology and the increased needs of applications. This led designers to invent new communication technologies such as Network-on- Chip (NoC) paradigm. Advances in integrated circuit fabrications even allowed three-dimensional NoC (3D-NoC) implementations. 3D-NoC architectures have more advantages than its 2D counterpart. 3D-NoCs have a lower area, higher efficiency and performance and lower energy consumption. However, they lack the design automation algorithms. An important design problem for a given application is mapping it on 3D-NoC topology. In this thesis, we propose a heuristic mapping algorithm, called CastNet3D, for mesh-based 3D-NoCs. The algorithm tries to utilize vertical links for communicating nodes as much as possible since they are faster and less energy consuming than horizontal ones. Simulated annealing based algorithm (SA3D) for the mapping problem is also proposed to compare the heuristic method with the metaheuristic method. CastNet3D has been compared against SA3D and two 2D-NoC algorithms on several benchmarks. The results show that CastNet3D obtains better mappings in terms of energy consumption most of the time in a very short time.