Uzamsal korelasyonları kullanarak eşitsizlik (derinlik) görüntülerini sıkıştıran verimli bir algoritma ve onun düşük maliyetli donanım mimarısı

This thesis proposes a low-cost Disparity Map (DM) compression algorithm and its hardware architecture for high resolution and high frame rate applications, where limited computational capacity and power consumption make it a significant challenge to run these applications in real-time. The proposed algorithm uses spatial correlations between neighboring disparity values and has two variants. The first variant, Single Neighbor (SN), encodes the current disparity using its left neighbor, whereas the second variant, Multiple Neighbor (MN), benefits from left and upper neighbors. The performance of the proposed algorithm is evaluated on DMs that are obtained using the most common low-cost stereo matching techniques for state of- the-art benchmarks. When evaluating the performance of the proposed compression algorithm, a median filter is applied to smooth out the DMs. After the median filter, the proposed algorithm with respect to original DM sizes, obtains 48% and 56% savings in memory space on the average for its SN and MN variants, respectively. Transferring DMs to the memory within the System-on-Chip (SoC) and transmitting them between SoCs in a compressed format will reduce the memory bandwidth usage and save power. Implementation results show that the proposed architecture can support 1920x1080 resolution at 60 fps on a low-cost FPGA while consuming very low area and power.