Architectural exploration of FPGAS and RTL2GDSII implementation of an FPGA

Growing design complexity and cost has forced designers to build programmability into System-on-Chip (SoC) designs to reduce the number of costly chip re-spins and amortize IC costs over several fabrications. Programmability of embedded FPGA (eFPGA) cores is one of a handful of design solutions to meet this challenge. However, creating a new FPGA is challenging because of the significant effort that must be spent on circuit design, layout, and verification. The time required until the tape-out is approximately 1 year of a large team from architecture definition to tape-out for a new FPGA, since the process is primarily done manually. Researchers have developed automated methodologies to overcome these barriers by modeling FPGA fabrics as Verilog netlists and generating layouts using ASIC automated design tools. Simplifying and shortening the design process would be advantageous since it could reduce the time to implement eFPGAs in SoCs while enhancing architecture explorations. For this purpose, OpenFPGA is introduced, an open-source framework that enables automated prototyping for FPGA architectures. To enable various design purposes, OpenFPGA integrates several popular open-source EDA tools, i.e., VTR and Yosys, with its own custom tools. In this work, we designed an FPGA using OpenFPGA framework and investigated the issues faced in the architecture selection, circuit design, layout, and verification of such a FPGA with Türkiye's domestic 250nm CMOS technology.