Çip araştırmaları için makine öğrenmesi temelli otonom kalite kontrolü ve karakteristik parametre çıkarımı

The flawless and correct functioning of high-end electronic devices is of utmost importance for consumers as well as for manufacturers. Although Metal-Oxide Semiconductor Field Effect Transistor (MOSFET) manufacturers use a variety of protocols and procedures in the development and production of high-tech devices, the integrated circuits are usually manufactured by third parties. The performance of the transistors used in integrated circuits can vary from batch to batch during manufacturing, and even samples within the same batch can have different performance characteristics. For applications in life-critical domains, the selection of the most fit for purpose components is vital. In addition, long quality control processes make it difficult for research institutes to reach faster and lower energy consumption chips. While this time-cost factor is reflected as a potential loss of revenue for research institutes, it may cause them to fall back in cutting-edge chip technology competition in today's world and cause a decrease in market size on a global scale. Therefore, while the developments for time-cost reductions directly affect positively on the industry and customers, they also pave the way for collaborations and academic contributions. In this thesis, we propose a new approach for the semiconductor industry to verify the quality of transistors and the extraction of characteristics of transistors.The I-V graphs of the components are evaluated by multiple Convolutional Neural Networks using visual data in a manner similar to expert evaluation, and then these Machine Learning architectures use a multi-model ensemble technique in which one architecture providing a negative output overrules the vote of the other architectures to ensure very stringent quality control. After the filtering process, we implemented a second model that we created in the CNN technique to extract the threshold voltage (Vth, the voltage point at which transistors switch from a non-conducting state to a conductive state), which is an important characteristic parameter to allow the researcher to get a general overview of devices. With these techniques, we can conduct a performance assessment of the printed chips and get a fast estimation of experimental chip architectures with their response to the input voltage. Our 2-step ML approach has been tested on approximately 2500 filtered devices. Our technique has achieved senior expert-level accuracy in filtering, and 50mV total error rate in not filtered dataset, and an 8mV total error rate in the filtered dataset by Vth extraction.