Congestion-aware adaptive routing algorithm design for 3D Network-on-Chip

New communication methods have become inevitable due to the continuous increase in the number of components on the integrated circuits. Designers, who prioritize performance, scalability, power consumption need better solutions. Network-on-Chip (NoC) architecture emerged as a solution to these requirements with its parallelism and scalability. As the technology advances in integrated circuit systems, cores can process more data and require better communication. As the number of cores increase, NoC desings need to have shorter average path than classical communication methods. 3D-NoC design has been proposed to meet these demands due to its architecture, speed, average path, and power consumption. However, the routing problems for 3D is more complicated than 2D version. Since deterministic algorithms encounter congestion problems, adaptive algorithms are able to distribute the traffic load to give better results. Motivated by the effectivenes of learning algorithms, in this thesis, we present a Q-Learning based routing algorithm for 3D-NoCs to solve this type of problems. In our algorithm, each router node maintains a Q-Table and updates it by receiving the traffic information from neighboring routers. We select the output port by using the state of the router and corresponding Q-Values. We have tested our proposed method with the deterministic XYZ and 3D elevator-first West-First algorithm under different traffic models and compared the results. We have observed an 8% average performance improvement compared to the other routing algorithms.