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Design and implementation of a kernelized correlation filters accelerator on zynq fpga via high-level synthesis of a custom dft block

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2024
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This study unveils a hardware-software co-design implementation of an accelerator for the Kernelized Correlation Filter (KCF) tracking algorithm, targeted at enhancing object tracking performance in embedded and real-time applications. The motivation for this research stems from the growing demand for efficient and real-time object tracking in various applications such as surveillance, autonomous vehicles, interactive systems, robotics, and automation. At the core of this implementation is the HighLevel Synthesis (HLS) of a custom hardware component for the Discrete Fourier Transform (DFT) operation, integrated into the Zynq heterogeneous platform. The innovation extends to the development of a custom combined DFT and inverse DFT Intellectual Property (IP), named CDFT, optimized specifically on the Programmable Logic (PL) side of the Xilinx ZCU102 FPGA. Concurrently, the remainder of the KCF algorithm operates on the Processing System side, supported by a customized Petalinux build. For comprehensive performance evaluation, the study introduces a driver for the CDFT IP alongside a user application, enabling the measurement of critical metrics including Center Location Error (CLE), Intersection over Union (IoU), and Frames per Second (FPS). This integrated approach yields significant performance enhancements, with the DFT accelerator demonstrating a remarkable 21x speedup over traditional software-based DFT implementations. At the algorithmic level, the KCF accelerator achieves a 6x speed increase with minimal precision loss, striking a balance between high accuracy and moderate speed. Compared to prior exclusively hardware-based implementations, this co-designed approach not only showcases superior accuracy but also presents avenues for further optimizations to augment its performance, setting a new benchmark in the domain of object tracking. Performance evaluation metrics, and the comparative results, offering a clear and concise overview of the study's contributions and achievements.

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Mustafa Yetiş

Bu Yayına Nasıl Atıf Yapılır

Mustafa Yetiş (Master Thesis). Design and implementation of a kernelized correlation filters accelerator on zynq fpga via high-level synthesis of a custom dft block, 2024, Ankara Yıldırım Beyazıt University.

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