Hardware based accelerator design for dram operations

Overall execution time on DRAM has vital impact on memory included system's performance. In this thesis, a new method which is called "SpareRow" is proposed. Spare row method is built on the key observation that high temporal locality exists among the rows of each subarray. By this observation, the idea is developed on copying the repeatedly accessed row on spare row reduces DRAM execution time. Simultaneously enabling the DRAM cells which are on same subarray and hold same values reduces the access latency on memory operations. This method reduces operation times especially on sensing and precharging. It is purposed that to add an extra (spare) row to each subarray to selectively store a duplicate of one of the rows of the subarray according to the temporal locality. Control mechanism copies the rows which will be potentially used in short term. In case the additional row stores the data of the row to be accessed, SpareRow enables both the target row and its duplicate at the same time to complete the DRAM access with low latency. If the spare row is different from the accessed row, target row is activated and mechanism copies that row on spare row. SpareRow is evaluated on a large set of workloads. It is observed that it significantly reduces average DRAM access latency and thus improves overall system performance.