True random number generation and fault modeling methods for reduced-voltage SRAM devices

SRAM-based on-chip memories are crucial components for various computing devices including heterogeneous devices, e.g, GPUs, FPGAs, and ASICs to achieve high performance. Modern workloads such as Deep Neural Networks (DNNs) running on these heterogeneous fabrics depend highly on the on-chip memory architecture for efficient acceleration. One of the common methods to save energy is undervolting i.e., supply voltage underscaling below the nominal level. Such systems can be safely undervolted without incurring faults down to a certain voltage limit. This safe range is also called a voltage guardband. However, reducing voltage below the guardband level without decreasing frequency causes timing-based faults. In the first study of this thesis, we propose MoRS, a framework that generates the first approximate undervolting fault model using real faults extracted from experimental undervolting studies on SRAMs to build the model. We inject the faults generated by MoRS into the on-chip memory of the DNN accelerator to evaluate the resilience of the system under the test. MoRS has the advantage of simplicity without any need for high-time overhead experiments while being accurate enough in comparison to a fully randomly-generated fault injection approach. We evaluate our experiment in popular DNN workloads by mapping weights to SRAMs and measuring the accuracy difference between the output of the MoRS and the real data. Our results show that the maximum difference between real fault data and the output fault model of MoRS is 6.21%. In contrast, the maximum difference between real data and the random fault injection model is 23.2%. In terms of average proximity to the real data, the output of MoRS outperforms the random fault injection approach by 3.21x. True random number generators (TRNGs) rely on unpredictable physical entropy sources such as electrical noise, thermal noise, and clock jitters. However, not all computing devices are equipped with dedicated hardware to extract entropy from these sources. Thus, it is costly to provide true random number generation capability to computing systems via dedicated hardware. Prior works propose TRNGs that extract entropy from memory devices that are present in most computing systems. SRAM-based TRNGs have two major advantages over other memory-based mechanisms: they can (i) provide random numbers to every scale of computing systems as SRAM is used in all contemporary CMOS-based chips and (ii) enhance the security of the true random numbers because no one can snoop the random number transfers as SRAM is an on-chip memory. Although SRAM-based TRNGs are promising due to these advantages, existing SRAM-based TRNGs suffer from two key limitations: they 1) need frequent power cycling, causing prohibitively large latencies and low throughput, and 2) have a significant energy overhead. Our goal is to design an SRAM-based TRNG that overcomes these two key limitations. To this end, we propose our second contribution, TuRaN, a new high-throughput, energy-efficient, and low-latency SRAM-based TRNG. TuRaN leverages the key observation that reading SRAM cells results in random values when the supply voltage is reduced below the manufacturer-recommended threshold. TuRaN generates random numbers at high throughput by repeatedly accessing undervolted SRAM cells and then post-processing the resulting faults using the SHA-256 hash function. To demonstrate that TuRaN generates true random numbers, we conduct real-world experiments on two commercial off-the-shelf FPGA boards. We evaluate the quality of the random numbers generated by TuRaN using widely-adopted NIST STS and observe that TuRaN passes all tests. TuRaN generates true random numbers with (i) an average (maximum) throughput of 1.6Gbps (1.812Gbps), (ii) 0.11nJ/bit energy consumption, and (iii) 278.46us latency. TuRaN outperforms the state-of-the-art SRAM-based TRNGs by 2.26x, 5.09x, and 5.39x throughput, energy efficiency, and latency, respectively.