Tag simplification: Achieving power efficiency through reducing the complexity of the wake up logic

The most important structure of an out of order processor, besides the reorder buffer which reorganizes the program flow, is the issue queue. The processor places the instructions in the issue queue after fetching them from memory, decoding them and applying other transformations. In this queue, instructions wait for their source data to be ready. Instructions which have both sources ready are assigned to execution units, and their results are written to the register file after their execution completes. Each result producing instruction broadcasts the register number of its result to the issue queue to inform following instructions that depend on this value. Every instruction in the issue queue compares their unavailable source operands with these broadcasted register numbers using a comparator and sets a ready bit for the source if the comparator matches. The issue queue, which handles many comparison, write and read operations every clock cycle, is one of the most power consuming components in a contemporary microprocessor core. Digital circuits have two types of power consumption: dynamic power consumption and static power consumption. Dynamic power consumption occurs due to transistors turning on and off and capacitors in the intermediate nodes being charged and discharged. Static power consumption occurs due to current leakage between the input voltage and ground of transistors, even when no operation occurs in the processor. Gradually shrinking transistor dimensions have increased the static power consumption due to current leakage, increasing the ratio of static power consumption to almost 50% at high temperatures.This thesis proposes techniques to reduce the dynamic and static power consumption of the issue queue, one of the most power consuming components in the processor. The proposed methods move the complexity of the adress comparison circuits of the issue queue to the earlier stages of the pipeline to reduce dynamic power consumption. Register numbers stored in the issue queue will be grouped and the register queue will be divided into more than one piece to compare only a certain width of register numbers within that piece to decrease dynamic power consumption. Using this method, a significant number of transistors and bits can be removed from the issue queue, decreasing both power consumption and latency. The complexity, power consumption and latency is moved to the front of the processor where they could be done faster.