A fair and secure cache architecture for multi-threaded processors

Hardware security gained more attention due to the widespread use of cloud computing and remote execution, where multiple executions share a computer's resources. It is possible to extract confidential information such as cryptographic keys through cache-based side-channel attacks as in Meltdown and Spectre attacks, and as a result, secure cache architectures have become one of the hot research topics in the computer architecture field, today. These architectures come with an inevitable performance penalty since there is always an overhead for hiding information from the attackers. Subsequently, the performance degradation is traded off with the improvement in security. In this thesis, we analyze cache-based side-channel attacks, and the performance deterioration of the existing architectures and come up with a new solution which improves the fairness of the general framework. We propose a secure cache mechanism that respects fairness among the competing threads within a processor. We evaluate FairSDP architecture in 4-threaded and 8-threaded processors. As a result, we show that we can achieve up to 8.7 percent performance improvement over the baseline and 9.2 percent better performance compared to the static partitioning on the average, in an 8-threaded system. We also achieve almost identical results in terms of the fairness metric compared to a non-secure dynamic cache partitioning scheme.