FFT ve FHT algorıtmaları için uygulamaya özgü komut kümeli işlemci tasarımı

Orthogonal Frequency Division Multiplexing (OFDM) is a multicarrier trans-mission technique which is used in many digital communication systems. Inthis technique, Fast Fourier Transformation (FFT) and inverse FFT (IFFT) arekernel processing blocks which are used for data modulation and demodulationrespectively. Another algorithm which can be used for multi-carrier transmissionis the Fast Hartley Transform algorithm. The FHT is a real valued transforma-tion and can give significantly better results than FFT algorithm in terms ofenergy efficiency, speed and die area. This thesis presents Application SpecificInstruction Set Processors (ASIP) for the FFT and FHT algorithms. ASIPscombine the flexibility of general purpose processors and efficiency of applicationspecific integrated circuits (ASIC). Programmability makes the processor flexibleand special instructions, memory architecture and pipeline makes the processorefficient.In order to design a low power processor we have selected the recently pro-posed cached FFT algorithm which outperforms standard FFT. For the cachedFFT algorithm we have designed two ASIPs one having a single execution unitiiiand the other having four execution units. For the FHT algorithm we havederived the cached FHT algorithm and designed two ASIPs; one for the FHTand one for the cached FHT algorithm. We have modeled these processors withan Architecture Description Language (ADL) called Language of Instruction SetArchitectures (LISA). The LISATek processor designer, generates the softwaretool chain (assembler, linker and instruction set simulator) and HDL code of theprocessor from the model in LISA automatically. The generated HDL code isfurther synthesized into gate-level description by Synopsis Design Compiler with0.13 micron technology library and then power simulations are performed. Thesingle execution unit cached FFT processor have been shown to save 25% of en-ergy consumption as compared to an FFT ASIP. The four execution unit cachedFFT processor on the other hand runs faster up to 186%. The ASIP designedfor the developed cached FHT algorithm runs almost two times faster than theASIP for the FHT algorithm.Keywords: FFT, cached FFT, FHT, cached FHT, Applicattion Specific Instruc-tion Set Processor, OFDMiv