FPGA based PLC FSK modem design and simulation

Communication and data transmission methods have a very important place today. With the development of technology, studies on alternative communication techniques are increasing. Power line communication is one of these alternatives. In addition, it is necessary for the design of these alternative communication methods to be flexible, easily testable and implementable so that the designs can be realized faster and more practically. At this point, field programmable door arrays meet these needs due to their structure. In this thesis, a FSK modem to be used for power line communication in the frequency range of 100-500 kHz on field programmable gate arrays has been designed and this design has been tested and simulated. Vivado interface and VHDL hardware definition language were used for the design and simulation studies. As a result of the simulations, it has been observed that the information sign applied to the input of the design is recovered at the output.