Fully random access differential lookup tables

Lookup Tables (LUTs) are often used to implement complex functions in hardware and software design to achieve low latency in computation of complex functions compared to algebraic implementations. However, the area of a LUT grows exponentially with the bitwidth of the input. This thesis presents a novel area-efficient and parameterized logic microarchitecture that behaves identical to a Conventional LUT (ConvLUT) implementing a continuous function. Six different architectures are implemented, all architectures keep a down-sampled version of the original LUT. Skipped LUT entries are replaced with one of the following; differential LUT entries, encoded differential LUT entries, or a method we called zone folding. These three architectures are also implemented by storing differences of differential LUT entries. By employing some combinational logic circuitry, all architectures can mimic a ConvLUT with a slight compromise in latency. The proposed architectures are fully random access, and are named as "Fully Random Access Differential LUT" (FR-dLUT). Later, multipartite tables method is combined and improved with the proposed architectures. In order to evaluate area and performance of FR-dLUT, all its variants for sine and 2x functions are coded in Verilog, verified, synthesized, and implemented on FPGA. Results are compared to the state-of-the-art in terms of area and performance.