Gerçek zamanlı video işleme algoritmalarının uygulanması için araç ve teknikler

Hardware implementation of video processing algorithms, which are usually real-time by nature, need architectural exploration so that we achieve the required performance with minimal cost. In addition, the video algorithm to be implemented may need to be used with different frames-per-second and resolution in different applications. Hence, we usually need to design a parameterized IP block instead of a fixed design. Also, during the hardware design process, the requirements fed from the algorithms team may change as well as the algorithm itself. As a result of these, hardware implementation iterations need to be as fast as the algorithms development iterations. This is only possible with the use of tools and techniques specifically geared towards hardware design generation for video processing. The tools and techniques discussed in this dissertation include host software, FPGA interface IP, HLS, RTL generation tools, an architectural estimation tool, flow based verification approach, and logic synthesis automation as well as architectural concepts (e.g., nested pipelining). The architectural estimation tool estimates many design metrics. These metrics are area, throughput, latency, DRAM usage, interface bandwidth, temperature, and compilation time. While we explain the above tools and techniques within a specific use case, namely, optical flow, we also present results from another use case, image fusion. Using our methodology and tools, we were able to design and bring up to 11 versions of optical flow and 3 versions of image fusion on 3 different FPGAs from 2 different vendors. The first version of these designs (hence the generators) took several months; however, the subsequent design versions each took a few days with a few people. In the case where only architectural trade-off is needed, we were able to generate and synthesize around one thousand designs in a single day on a 48-core server.